1. Field of the Invention
The present invention relates to a semiconductor memory and a production method thereof, and, more specifically, to a dynamic random access memory (DRAM) and a production method thereof.
2. Description of the Related Art
In recent years, information possessing systems including a computer have become very popular, which brings about a great expansion of the market for semiconductor memories. The market is still expanding at a great rate. In this application field, the semiconductor memory is required to have a great memory capacity, and to operate at a high speed. In view of the above, research and development are being continued to achieve a semiconductor memory having a greater memory capacity, higher operation speed, and higher reliability.
There are various types of semiconductor memories. Among them, there is a DRAM which is a semiconductor memory capable of reading and writing information in a random fashion. A DRAM comprises a memory cell array for storing a large amount of information, and a peripheral circuit for selecting a memory cell, which is a unit memory circuit, and for controlling the input/output operation between the memory and an external system.
FIG. 15 is a block diagram illustrating a configuration of a common DRAM. As shown in the figure, DRAM 50 comprises: a memory cell array 51 for storing information to be stored; a row and column address buffer 52 that receives an address signal from the outside wherein the address signal specifies a memory cell to be selected; a row decoder 53 that extracts a row address of a memory cell to be selected from the address signal; a column decoder 54 that extracts a column address of a memory cell to be selected from the address signal; a sense refresh amplifier 55 for amplifying a signal in reading information from a memory cell; a data-in buffer 56 for receiving an information signal from outside; a data-out buffer 57 for outputting a stored information signal; and a clock generator 58 for generating a basic control signal.
The memory cell array 51 occupies a large area on a semiconductor chip. In the memory cell array 51, a plurality of memory cells each storing unit information are arranged in a matrix fashion.
FIG. 16 illustrates an equivalent circuit of four memory cells wherein each memory cell is capable of storing one-bit information. As shown in the figure, the memory cell array 51 includes a plurality of word lines WL extending in the X-row direction, and a plurality of pairs of bit-lines (BL, BL) extending in the Y-column direction. Memory cells M are formed in the vicinities of word and bit lines. Each memory cell M comprises a capacitor for storing information charge, and an insulated gate field effect transistor or a MIS (Metal Insulator Semiconductor) transistor. This type of memory cell has a simple configuration, and thus is used very broadly. In FIG. 16, a pair of bit lines (BL, BL) are disposed parallel to each other toward a sense refresh amplifier 55 in a folded bit line scheme.
A conventional semiconductor memory is configured in such a manner described above, and operates as follows.
In FIG. 15, data are stored in the N (n.times.m) bit memory cell array 51. Address information specifying a memory cell where information is to be read or written is stored in the row and column address buffer 52. The row decoder 59 selects a word line (from n word lines) thereby electrically connecting m bit memory cells to the sense refresh amplifier 55 through bit lines. On the other hand, the column decoder 54 selects a pair of bit lines (from m pairs of bit lines) thereby connecting a sense refresh amplifier 55 to a data-in buffer 56 or a data-out buffer 57. As described above, one memory cell is chosen from the N bit memory cell array 51 according to the address signal.
Furthermore, as shown in FIG. 16, the gate electrode of each MIS transistor is connected to a word line (WL). One of the source/drain electrodes of each MIS transistor is connected to an electrode of a capacitor C, and the other electrode is connected to either bit line of a pair of bit lines, that is, either BL or BL. When a word line WL is selected according to a specified address and thus a predetermined voltage is applied to the word line WL, a MIS transistor is turned on and charge corresponding to the voltage on a bit line BL or BL flows into a capacitor C and is stored in it. To read data, a predetermined voltage is applied to a selected word line WL thereby turning on a MIS transistor. Then, the charge stored in a capacitor C is discharged through a bit line BL or BL.
FIG. 17A illustrates an example of memory cell structure of a conventional DRAM disclosed in "A CAPACITOR-OVER-BIT-LINE (COB) CELL WITH A HEMISPHERICAL-GRAIN STORAGE NODE FOR 64Mb DRAMs" (M. Sakao et al., IEEE IEDM Technical Digest pp.655-658,1990). In this memory cell M, MIS transistors are disposed in a flat area of the primary surface of a semiconductor substrate, and capacitors are formed in a stacked fashion.
In such a memory cell, two memory cells are disposed in a region surrounded by an isolation oxide film 10 on the primary surface of the p-type semiconductor substrate 1 in such a manner that both memory cells share one bit line contact 8. Gate electrodes 15c of n-channel MIS transistors are disposed from side to side via the bit line contact 8. Each n-channel MIS transistor comprises a gate electrode 15c disposed on the p-channel silicon substrate 1 via a thin gate dielectric film 17, and further comprises n-type source/drain impurity diffusion layers 18 disposed at each side of the gate electrode 15c. One of n-type source/drain impurity diffusion layers 18 is connected to bit line 6, and the other n-type source/drain impurity diffusion layer 18 is connected to a storage node (an information charge storage layer) 7 that forms a capacitor.
The gate electrode 15c of the MIS transistor also serves as a first word line extending from the gate electrode 15c wherein the word line is arranged in a folded bit line scheme. Therefore, the first word line 15c extends over the isolation oxide film 10 such that it connects gate electrodes of adjacent memory cells M to each other. A bit line 6 is located in a higher layer than the first word line 15c, wherein the bit line is connected to the bit line contact 8. A second word line 15b of aluminum is in a still higher layer than the bit line layer wherein the second word line 15b is connected in parallel to the first word line 15c.
In a semiconductor memory such as that described above, if the integration density is increased from a 64-Mbit DRAM such as that shown in FIG. 17A to a 256-Mbit DRAM or further to a 1-Gbit DRAM, the area of each memory cell occupying a semiconductor substrate must be reduced.
However, reduction of the area of each memory cell is limited, since the capacitance of a capacitor should be greater than a certain value. To prevent erroneous operation of a memory circuit, or soft errors, due to the generation of electron-hole pairs in a semiconductor substrate induced by alpha-particles in a DRAM package, the capacitor should have a capacitance of at least 40 fF.
One known technique to achieve such a large capacitance in a small area of a semiconductor substrate is to employ a capacitance structure such as a stacked-type capacitor which has a cross section such as that shown in FIG. 17B (17A), in which a second storage node 7a, called a hemispherical grain (HSG) poly-silicon storage node, is added to a first common storage node 7. However, the memory cell according to this technique has so complicated a structure that an increase in the number of production process steps and thus a reduction in production yield occur, which leads to an increase in production cost.
Furthermore, this technique also has problems due to short-channel effects as well as narrow-channel effects which occur in channel regions of MIS transistors. That is, if the channel length is reduced, then the threshold voltage becomes lower and dependence of the variation in the threshold voltage on channel length becomes greater. Furthermore, the threshold voltage increases due to the lateral expansion of a depletion region, which is called a narrow-channel effect. In a pinch-off region near the end of drain region, hot carriers are generated by impact ionization. These hot carriers may cause long-term degradation in characteristics of a transistor, which is known as the hot carrier effect. This causes a problem with reliability. If the channel length or channel width is reduced to a submicron order, problems occur in the channel region as described above. As a result, it is very difficult to reduce the device size.